Clock Generator for Wide-band Delta-Sigma ADCs - Hoang-Phuong, Chi; Nguyen-Thu, Ngoc; Nguyen-Van, Quyet; Nguyen-Minh, Tien; Nguyen-Duc, Minh; Pham-Nguyen, Loan (Old Journal, 2017)
In this paper, a new design of clock generator applied for high-speed and wide-band receiver is discussed. The circuit generates 4 local oscillators (LO) at frequency fLO = 0.5*fCLK from input clock frequency fcLK, which is in the range of 800 MHz-12 GHz; and 8 phases Ф, by selecting 3 bits S0 S1 S2 at sampling frequency fs = 400 MHz-425 MHz. LO clocks and phases are designed to satisfy the strict requirements such as falling/rising time, non-overlapping, pulse width and synchronization, power consumption (