A Low Area AES Encryption Core with Silicon Demonstration in 180nm CMOS Process
Main Article Content
Abstract
This paper presents a low area, low power AES encryption core with the combination of several optimized components in the AES core and some modifications in the core architecture for emerging wireless networks and IoT systems. The detail results of area-speed-power trade-offs in the proposed AES core design are also presented and discussed. The implementation and chip measurement results in 180nm CMOS technology show that the proposed AES encryption core can reduce the area and power consumption significantly. The power consumption of the proposed AES encryption core is only 7.1 µW/MHz and the area is 2.3 kgates which are much lower than other AES cores presented in literature.
Keywords
AES, ASIC, low area, low power, CMOS
Article Details
References
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[2] J. Dofe, J. Frey, Q. Yu, Hardware security assurance in emerging IoT applications, IEEE Inter. Symp. Cir. and Syst. (ISCAS), pp. 2050-2053, 2016.
[3] National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES), FIPS Publication 197, Nov. 2001.
[4] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, A compact Rijndael hardware architecture with S-box optimization, Proc. ASIACRYPT 2001, pp.239-254, Dec. 2001.
[5] P. Hamalainen, T. Alho, M. Hannikainen, T.D. Hamalainen, Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core, Proc. 9th EUROMICRO Conf. Digital System Design: Architectures, Methods and Tools (DSD2006), pp.577-583, 2006.
[6] D. Canright, A very compact S-box for AES, Proc. 7th Int. Workshop on Cryptographic Hardware and Embedded Systems (CHES2005), pp.441-455, Sep. 2005.
[7] D. Canright and L. Batina, A Very Compact Perfectly Masked S-Box for AES, Proc. ACNS 2008, vol. 5037, LNCS, pp.446-459, Springer, 2008.
[8] T. Jarvinen, P. Salmela, P. Hamalainen, J. Takala, Efficient byte permutation realizations for compact AES implementations, Proc. 13th European on Signal Processing Conference, pp.1-4, Sep. 2005.
[9] K. Munusamy, C. Senthilpari, D.C.K. Kho, A low power hardware implementation of S-Box for Advanced Encryption Standard, Proc. 11th International Conference on Electrical Engineering/ Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), pp.1-6, May 2014.
[10] Mathew Sanu et al., 340 mV-1.1 V, 289 Gbps/W, 2090-gate nanoAES hardware accelerator with area-optimized encrypt/decrypt GF (2^4)^2 polynomials in 22 nm tri-gate CMOS, IEEE Journal of Solid-State Circuits 50.4, pp. 1048-1058, 2015.
[11] T. Good and M. Benaissa, 692-nW advanced encryption standard (AES) on a 0.13-µm CMOS, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.18, no.12, pp.1753-1757, Dec. 2010.
[12] Wenfeng Zhao, Yajun Ha, Massimo Alioto, AES Architectures for Minimum-Energy Operation and Silicon Demonstration in 65nm with Lowest Energy per Encryption, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-4, May 2015.