Heuristics for Dynamic Mapping of Quality Adjustable Applications on NoC-based Reconfigurable Platforms
Main Article Content
Abstract
Network on Chip and FPGA-based reconfigurable Systems on Chip are a new trend to provide high performance, flexibility, reducing cost and time to market for the embedded systems. The problem of mapping quality adjustable applications onto heterogeneous NoC-based reconfigurable platforms at run-time with resource constraints while ensuring the maximum overall quality of service of the applications is a big challenge. In this paper, an efficient mapping technique is proposed to solve this problem which consists of a near convex region selection strategy and a dynamic heuristic mapping algorithm. Simulation results show that the proposed technique is very flexible and more than 43% average overall QoS can be achieved compared to some existing solutions. Besides, this technique allows new applications to be easily added to the system in the future.
Keywords
Network on Chip, dynamic mapping, reconfigurable region, quality level, heterogeneous
Article Details
References
[1] http://www.xilinx.com/products/silicon-devices/soc.html
[2] Kim, Dong-Jin, Yeon-Jeong Ju, and Young-Seak Park, "An Implementation of SoC FPGA-based Real-time Object Recognition and Tracking System," IEMEK Journal of Embedded Systems and Applications, vol. 10, no. 6, pp. 363-372, 2015.
[3] Luo, Junwen, Graeme Coapes, Terrence Mak, Tadashi Yamazaki, Chung Tin, and Patrick Degenaar, "Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System," IEEE transactions on biomedical circuits and systems, vol. 10, no. 3, pp. 742-753, 2016.
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[14] Chen. L. Chou, U. Y. Ogras and R. Marculescu, "Energy-and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 27, по. 10, pp. 1866-1879, 2008.
[15] Chen. L. Chou and R. Marculescu, "User-aware dynamic task allocation in networks-on-chip." 2008 Design, Automation and Test in Europe. IEEE, 2008.
[16] M. Haghbayan, A. Kanduri, A. Rahmani, P. Liljeberg, A. Jantsch, and H. Tenhunen, "MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip," in Proceedings of the 9th International Symposium on Networks-on-Chip, p. 26. ACM, 2015.
[17] N. P. Ngoc, G. Lafruit, S. Vernalde, and R. Lauwereins, "Real-Time 3D Applications on Mobile Platforms With Run-Time Reconfigurable region Accelerator," In Proceedings of the International Conference on Computer Visions and Graphics, ICCVG, 2002, pp. 582-588.
[18] E. Carvalho, N. Calazans, and F. Moraes, "Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs," in 18th IEEE/IFIP International Workshop оп Rapid System Prototyping. 2007. RSP 2007, 2007. pp. 34-40.
[19] R. P. Dick, D. L. Rhodes and W. Wolf, "TGFF: task graphs for free," Proc. Intl.
[2] Kim, Dong-Jin, Yeon-Jeong Ju, and Young-Seak Park, "An Implementation of SoC FPGA-based Real-time Object Recognition and Tracking System," IEMEK Journal of Embedded Systems and Applications, vol. 10, no. 6, pp. 363-372, 2015.
[3] Luo, Junwen, Graeme Coapes, Terrence Mak, Tadashi Yamazaki, Chung Tin, and Patrick Degenaar, "Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System," IEEE transactions on biomedical circuits and systems, vol. 10, no. 3, pp. 742-753, 2016.
[4] Flasskamp, Martin, Gregor Sievers, Johannes Ax, Christian Klarhorst, Thorsten Jungeblut, Wayne Kelly, Michael Thies, and Mario Porrmann, "Performance estimation of streaming applications for hierarchical MPSoCs." In Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, ACM 2016.
[5] Leibo, L. I. U., W. A. N. G. Dong, C. H. E. N. Yingjie, Z. H. U. Min, Y. L. N. Shouyi, and W. E. L Shaojun, "An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform." IEICE transactions on Information and Systems 99, no. 5, pp. 1285-1295, 2016.
[6] Hsiao, Pei-Yung. Shih-Yu Lin, and Shih-Shinh Huang, "An FPGA based human detection system with embedded platform," Microelectronic Engineering 138, 2015, pp. 42-46.
[7] Pang, Ke., Virginie Fresse, Suying Yao, and Otavio Alcantara De Lima, "Task mapping and mesh topology exploration for an FPGA-based network on chip," Microprocessors and Microsystems 39, no. 3, pp. 189-199, 2015.
[8] L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," Computer (Long. Beach. Calif), vol. 35, no. 1, pp. 70-78, 2002.
[9] R. Kumar, D. M. D. M. Tullsen, P. Ranganathan, N. P. N. P. Jouppi, and K. I. Farkas, "Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance," in Proceedings of the 31st annual international symposium on Computer architecture, 2004, pp. 64-75.
[10] M. S. Abdelfattah, A. Bitar, and V. Betz, "Take the Highway: Design for Embedded NoCs on FPGAs," in Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015, pp. 98-107.
[11] N. Van Cuong, N. T. Bang, L. D. Tuyen, and P. N. Nam, "Dynamic Mapping of Quality Adjustable Applications on NoC-based Reconfigurable Platforms," in The International Conference оп Advanced Technologies for Communications (ATC), 2016, pp. 321-326.
[12] L. Ost, G. M. Almeida, M. Mandelli, E. Wachter, S. Varyani, G. Sassatelli, L. S. Indrusiak, M. Robert, and F. Moraes, "Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling," in 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 Proceedings, 2011, pp. 1-8.
[13] A. K. Singh, T. Srikanthan, A. Kumar, and W. Jigang, "Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms." J. Syst. Archit., vol. 56, no. 7, pp. 242-255, 2010.
[14] Chen. L. Chou, U. Y. Ogras and R. Marculescu, "Energy-and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 27, по. 10, pp. 1866-1879, 2008.
[15] Chen. L. Chou and R. Marculescu, "User-aware dynamic task allocation in networks-on-chip." 2008 Design, Automation and Test in Europe. IEEE, 2008.
[16] M. Haghbayan, A. Kanduri, A. Rahmani, P. Liljeberg, A. Jantsch, and H. Tenhunen, "MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip," in Proceedings of the 9th International Symposium on Networks-on-Chip, p. 26. ACM, 2015.
[17] N. P. Ngoc, G. Lafruit, S. Vernalde, and R. Lauwereins, "Real-Time 3D Applications on Mobile Platforms With Run-Time Reconfigurable region Accelerator," In Proceedings of the International Conference on Computer Visions and Graphics, ICCVG, 2002, pp. 582-588.
[18] E. Carvalho, N. Calazans, and F. Moraes, "Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs," in 18th IEEE/IFIP International Workshop оп Rapid System Prototyping. 2007. RSP 2007, 2007. pp. 34-40.
[19] R. P. Dick, D. L. Rhodes and W. Wolf, "TGFF: task graphs for free," Proc. Intl.