Clock Generator for Wide-band Delta-Sigma ADCs
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Abstract
In this paper, a new design of clock generator applied for high-speed and wide-band receiver is discussed. The circuit generates 4 local oscillators (LO) at frequency fLO = 0.5*fCLK from input clock frequency fcLK, which is in the range of 800 MHz-12 GHz; and 8 phases Ф, by selecting 3 bits S0 S1 S2 at sampling frequency fs = 400 MHz-425 MHz. LO clocks and phases are designed to satisfy the strict requirements such as falling/rising time, non-overlapping, pulse width and synchronization, power consumption ( <20 mW). The proposed clock generator is implemented in CMOS 65nm and simulated in Cadence at TT/85°C.
Keywords
Clock generator, Wide-band, ADC
Article Details
References
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[2] M. Englund., "A Programmable 0.7-to-2.7GHz Direct Receiver in 40nm CMOS," Solid-State Circuits, IEEE Journal of, vol. PP, no. 12, pp. 1-12. 2015.
[3] M. T. Nguyen, C. Jabbour and V. T. Nguyen, "A flexible receiver using ΔΣ modulation," 2016 IEEE International Symposium on Circuits and Systems (ISCAS). Montreal, QC, 2016. pp. 1470-1473.
[4] Francesco Barale "Frequency Dividers Design For Multi-GHz PLL Systems", Georgia Institute of Technology, page 13-33, August. 2008