An FPGA-Based SoC Implementation of the CRYSTALS-Dilithium Post-Quantum Digital Signature Scheme

Abstract

The rapid advancement of quantum computing threatens the long-term security of conventional public-key cryptosystems, motivating the development of practical post-quantum cryptographic solutions. Among the algorithms standardized by the National Institute of Standards and Technology, CRYSTALS-Dilithium has emerged as a leading lattice-based digital signature scheme due to its strong security guarantees and implementation efficiency. However, efficient realization of CRYSTALS-Dilithium on resource-constrained embedded platforms remains challenging. This paper presents an FPGA-based System-on-Chip architecture for the CRYSTALS-Dilithium post-quantum digital signature scheme. The proposed design adopts a hardware–software co-design approach in which computationally intensive modules, including matrix expansion, SHAKE-256 hashing, and polynomial vector operations, are implemented in hardware to exploit FPGA parallelism while maintaining reasonable resource utilization. The architecture is implemented on a Xilinx Artix-7 (Basys-3) platform and evaluated using the NIST security level 5 parameter set at an operating frequency of 100 MHz. Experimental results show that the average key generation time is 2653.63 ms, while signing and verification require 2.695 ms and 1.105 ms, respectively. Performance analysis indicates that key generation dominates the total execution time, approximately 99.85%, primarily due to the complexity of the key generation process and the current non-optimized UART data transfer mechanism. These results demonstrate the functional feasibility of the proposed low-cost FPGA SoC architecture and provide a practical baseline for future performance and resource optimization of CRYSTALS-Dilithium accelerators in embedded post-quantum cryptographic systems.